Efficient Resource-Aware Neural Architecture Search with a Neuro-Symbolic Approach

Integrated Optical Phased Arrays for on-Chip Communication

Technology-Aware Drift Resilience Analysis of RRAM Crossbar Array Configurations

The challenge of classification confidence estimation in dynamically-adaptive neural networks

Exploring Process-Voltage-Temperature Variations Impact on 4T1R Multiplexers for Energy-aware Resistive RAM-based FPGAs

On-chip wireless interconnection through reconfigurable optical phased arrays

An Asynchronous Soft Macro for Ultra-Low Power Communication in Neuromorphic Computing

Exploring Software Models for the Resilience Analysis of Deep Learning Accelerators: the NVDLA Case Study

Comparative Analysis and Optimization of the SystemC-AMS Analog Simulation Efficiency of Resistive Crossbar Arrays

Reconfigurable on-chip wireless interconnections through optical phased arrays (Invited)

Cross-Layer Hardware/Software Assessment of the Open-Source NVDLA Configurable Deep Learning Accelerator

An Interconnect-Centric Approach to the Flexible Partitioning and Isolation of Many-Core Accelerators for Fog Computing

A Low-latency and flexible tdm noc for strong isolation in security-critical systems

PSION: Combining Logical Topology and Physical Layout Optimization for Wavelength-Routed ONoCs

CustomTopo: A topology generation method for application-specific wavelength-routed optical NoCs

Correlating Power Efficiency and Lifetime to Programming Strategies in RRAM-Based FPGAs

Wavelength-Routed Optical Networks-on-Chip: Design Methods and Tools to Bridge the Gap Between Logic Topologies and Physical Ones in 3D Architectures

Understanding the Design Space of Wavelength-Routed Optical NoC Topologies for Power-Performance Optimization

Interfacing 3D-stacked electronic and optical NoCs with mixed CMOS-ECL bridges: A realistic preliminary assessment

Special session on overcoming reliability and energy-efficiency challenges with silicon photonics for future manycore computing